This invention relates to testing integrated circuits in a data processing system by scanning known input data to selected stimulus points in the integrated circuit and scanning correspondingly produced result data from selected observation points in the integrated circuit.
Scannable integrated circuits generally comprise one or more "scan chains" for applying known stimulus (i.e., test) data to the functional circuitry of the integrated circuit and observing data that results from one or more subsequent normal operating cycles. The scan chains are also useful for initializing the integrated circuit.
Some scannable integrated circuits include a scan chain comprising a set of latches interposed between the primary input, output and input/output (I/O) pads and the functional circuitry. The latches are transparent to data during normal operation and are configurable as serial shift registers for scanning. The serial data inputs and outputs of the latches are interconnected to form a single serial shift register, the input and output of which are connected to a pair of pads. This scan chain is known as a "pad ring" scan chain. The pad ring scan chain is useful for testing and/or initializing functional circuitry available to the primary input, output and I/O pads.
Conventional scan techniques, such as those described in Zasio, U.S. Pat. Nos. 4,495,628, 4,495,629, and 4,587,480, typically test the integrated circuit at the wafer level, that is, before the integrated circuit is packaged and installed in the system, for example, as part of a printed circuit board. Thus, the pads of the integrated circuit are unconnected to other devices, and the pad s scannable latches, when configured as shift registers, do not isolate the functional circuitry of the integrated circuit from the pads. Two different scannable latch configurations are used, one for input pads and one for output pads.